With the development of semiconductor devices, the operation speed of semiconductor devices is getting more increased. Due to the high-speed operation of the semiconductor device, a timing margin for a signal processing is much decreased. Although there is a difference between the architecture design and the really manufactured circuit in the operation-timing margin, this difference is not an important factor in the low-speed semiconductor device; however, in the high-speed semiconductor device, such a difference does not make it possible to carry out a normal operation.
In recent, when the high-speed semiconductor device is developed, a sample device which is directly manufactured by a mass production plane is required to verify an existence of an error between the architecture design and the sample device. If an amount of error is more than the expected margin, the designer of the sample should modify and adjust the architecture. This has a drawback in that the developing time of the high-speed semiconductor device is much longer than that of the low speed semiconductor device.
FIG. 1 is a block diagram of a data input part of a conventional semiconductor device and FIG. 2 is detailed circuit diagram of the data input part in FIG. 1.
First, referring to FIG. 1, the conventional semiconductor device includes: a DQS (Data Strobe Signal) pulse generator 10 receiving a DQS signal and producing a DQS pulse signal DQSP whenever the DQS signal is inputted from an external circuit; first and second timing adjustors 20 and 40 receiving and delaying data D0 and D1 and outputting the delayed data D0_D and D1_D, respectively; and first and second data latch circuits 30 and 50 respectively latching the delayed data D0_D and D1_D from the first and second timing adjustors 20 and 40 in response to the DQS pulse signal DQSP and transferring the latched data D0_L and D1_L to an internal circuit of the semiconductor device.
Referring to FIG. 2, the DQS pulse generator 10 has inverters I1 to I3 for inverting the DQS signal, a NAND gate ND1 for performing a NAND operation of the DQS signal and an output signal of the inverter I3 and an inverter I4 for inverting an output signal of the NAND gate ND1 and for outputting an inverted signal as the DQS pulse signal DQSP.
The first timing adjustors 20 has inverters I5 and I6, which are in series coupled to each other, for receiving the data D0, buffering the received data D0 and outputting the buffered data to the first data latch circuit 30 and a capacitor Cd coupled to both a ground voltage level VSS and an output terminal of the inverter I5 for delaying an output signal of the inverter I5 for a predetermined time.
First data latch circuit 30 includes: an inverter I7 for inverting the DQS pulse signal DQSP in order to produce a switching signal; a transfer gate T1 for transferring the delayed data D0_D in response to the DQS pulse signal DQSP and the inverted DQS pulse signal from the inverter I7; inverters I8 and I9 for latching the data from the transfer gate T1; an inverter I10 for inverting the latched data by the inverters I8 and I9; a transfer gate T2 for transferring an output of the inverter I10 in response to the DQS pulse signal DQSP and the inverted DQS pulse signal from the inverter I7; inverters I11 and I12 for latching the data from the transfer gate T2; and an inverter I13 for inverting the latched data by the inverters I11 and I12.
The second data timing adjustor 40 has the same scheme as the first data timing adjustor 20 and the first latch circuit 30 also has the same scheme as the second data latch circuit 50. The number of the data timing adjustors and the latch circuits are determined according to the number of data; however, in this invention, the number of data timing adjustors and the latch circuits is limited into two blocks as shown in FIG. 1.
FIG. 3 is a timing chart illustrating an operation of the data input part in FIG. 1. The DQS signal is a signal indicative of data input timing in a synchronous memory device. The DQS signal is kept in a high impedance state in a normal mode and it goes to a preamble state of a low voltage level before one clock period of the data input. The clocking of the DQS signal is performed in the preamble state in response to the data input timing and it goes to a postamble state of a low voltage state after all of data are inputted and thereafter it is kept in a high impedance state. Accordingly, the clocking of the DQS signal means that the data are currently inputted.
The first data timing adjustor 20 receives the data D0, delays the input data D0 through the capacitor Cd for a predetermined time, and outputs the delayed data D0_D to the first latch circuit 30. Whenever the DQS signal is clocked, the DQS pulse generator 10 generates the DQS pulse signal DQSP and output the DQS pulse signal DQSP to the first and second data latch circuits 30 and 50.
The first latch circuit 30 latches the delayed data D0_D from the first data timing adjustor 20 in response to the DQS pulse signal DQSP from the DQS pulse generator 10. Accordingly, the delayed data D0_D is latched in the first data timing adjustor 20 for one period of the DQS pulse signal DQSP and the latch data D0_L may be transmitted to an internal circuit of the memory device for one period of the DQS pulse signal DQSP.
The reason why the data D0 is transmitted to the first data latch circuit 30 after it is delayed in the capacitor Cd of the first data timing adjustor 20 is that it takes longer time to generate the DQS pulse signal DQSP using the DQS signal and to transmit it to the first latch circuit 30 than to transmit the data D0 to the first latch circuit 30.
A DQS pin receiving the DQS signal is typically prepared every eight data pins. Further, the time the DQS pulse signal DQSP is transmitted to the data latch circuit is longer than the time the data signal is transmitted to the data latch circuits because the DQS pulse signal DQSP generated in the DQS pulse generator 10 is transmitted to eight data latch circuits.
Accordingly, the first data timing adjustor 20 delays the input data for a predetermined time and outputs the delayed data to the first data latch circuit 30 in order for the normally input data to be latched in the first data latch circuit 30. The capacitors Cd in the first and second data timing adjustors 20 and 40 have capacitance which is associated with the time the DQS pulse signal DQSP is transmitted to the first data latch circuit 30 and the data signal is transmitted to the first data latch circuit 30.
However, with the high speed performance of the memory device, the operating speed is getting higher and the data input margin, such as a set-up time tDS and data threshold time tDH, is fixed to a specific time or is getting smaller. Accordingly, if the real memory device is tested after the manufacture, it has a different timing margin from the designed one. Further, an error, which is caused by a variation of the capacitance of the capacitor Cd in the data timing adjustor, is also an important factor for the high-speed memory device.
In case that an error between the designed AC parameters, such as a data set-uptime tDS and data threshold time tDH, and the really tested AC parameters is larger than a allowable margin, the capacitance of the capacitor Cd in the data timing adjustor is controlled and the memory device is manufactured again based on the this controlled capacitance. As a result, the higher the operation speed of the memory device is, the longer the developing time of the memory device is.